Apparatus and method for information processing enabling fast access to program

ABSTRACT

A main memory stores cache blocks obtained by dividing a program. At a position in a cache block where a branch to another cache block is provided, there is embedded an instruction for activating a branch resolution routine for performing processing, such as loading of a cache block of the branch target. A program is loaded into a local memory in units of cache blocks, and the cache blocks are serially stored in first through nth banks, which are sections provided in the storage area. Management of addresses in the local memory or processing for discarding a copy of a cache block is performed with reference to an address translation table, an inter-bank reference table and a generation number table.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an information processing technique,and particularly to an information processor that is provided with amemory having a hierarchical structure, and an information processingmethod applicable to the information processor.

2. Description of the Related Art

Due to the advances in information processing techniques of recentyears, a wide variety of functions can be easily implemented on aninformation processor by activating, for example, software recorded inCD-ROMs or other recording media, or software downloaded from servers onnetworks. Under such circumstances, efficient and high-speed processingof programs has continued to be an important issue.

To enable high-speed processing, there needs to be not only improvementin performance of processors but also improvement in data transfer ratebetween units in an information processor, such as between processorunits or between a processor unit and a memory. One technique forenabling a processor's fast access to data or a program stored in amemory is to hierarchize the memory using a cache memory. Generally, acache memory has a capacity smaller than that of a main memory andenables fast access. By storing frequently accessed data in a cachememory, the number of access to the main memory can be decreased,thereby reducing the overall time required for data access. Also in amultiprocessor system comprising multiple processors, local memoriesprovided in the respective processors enable fast access to a greateramount of data.

In order for a processor to process a program faster, the processor alsoneeds to access the machine code faster. However, since a memory forenabling fast access, i.e. a high-speed memory, generally has a smallcapacity, programs often cannot be stored entirely therein depending onthe size of the program. In such case, a programmer needs to manuallydivide the program into multiple modules and also describe a program forloading such modules at appropriate times from the main memory into thehigh-speed memory.

SUMMARY OF THE INVENTION

The present invention has been made in view of such a problem, and ageneral purpose thereof is to provide a technique for enabling fast andefficient access to a program.

One aspect of the present invention relates to an information processor.The information processor comprises:

a main memory which stores a plurality of data blocks having connectionsaccording to a reference order in which the data blocks are referred to;a local memory which stores at least part of the plurality of datablocks copied thereinto; and a processor which performs processing byserially referring to the data blocks copied into the local memoryaccording to the reference order and which newly copies the data blockfrom the main memory into the local memory if necessary, wherein: anarea for storing the data blocks in the local memory comprises aplurality of sections; and, when there is a shortage of a storage areawithin the local memory into which a data block is newly copied, theprocessor discards the data blocks copied previously in units of thesections to ensure a new storage area, and stores in the local memory,with respect to each of the data blocks copied, reference destinationinformation on the storage area of a data block to be referred toposteriorly to the data block, so as to serially refer to the datablocks.

In the above, “having connections according to a reference order” meansthat the data blocks have connections between each other in terms of theorder in which the data block are referred to, such as the case whereafter a data block is referred to halfway or all the way, another datablock needs to be referred to. The situation of “having connectionsaccording to a reference order” includes, for example, the case wheretwo data blocks are positioned consecutively in the reference order, thecase where the reference destination returns or does not return to theoriginal data block, and the case where three or more data blocks haveconnections between each other. Since the relationships between datablocks are not restricted, such situation also includes both the casewhere a data block is referred to in order that another data block isreferred to, and the case where data blocks have no correlation butthere is an order in which the data blocks are to be referred to. Also,a “data block” may be program data, numerical data, image data or audiodata, or data obtained by dividing such data according to a given rule,or a combination of such data.

Another aspect of the present invention relates to an informationprocessing method. The information processing method comprises: storing,in a local memory, program data of a branch source in which a branchinstruction specifying an address in the local memory is described, andprogram data of a branch target which contains the address specified bythe branch instruction, and relating information on the storage area ofthe program data of the branch source in the local memory to the programdata of the branch target to store the information; and identifying,when the program data of the branch target is discarded, the programdata of the branch source on the basis of the information on the storagearea of the program data of the branch source in the local memory, andinvalidating the address specified by a branch instruction described inthe program data of the branch source.

Optional combinations of the aforementioned constituting elements, andimplementations of the invention in the form of methods, apparatuses,systems and computer programs may also be practiced as additional modesof the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will now be described, by way of example only, withreference to the accompanying drawings which are meant to be exemplary,not limiting, and wherein like elements are numbered alike in severalFigures, in which:

FIG. 1 is a diagram that shows the configuration of an informationprocessor according to an embodiment;

FIG. 2 is a diagram that schematically shows the structure of datastored in a local memory and a main memory in the embodiment;

FIG. 3 is a diagram that shows the configuration of a compiler forcreating a cache block and executing a branch resolution routine in theembodiment;

FIG. 4 is a diagram that schematically shows the structure of two cacheblocks stored in the main memory in the embodiment;

FIG. 5 is a diagram that schematically shows the structure of copies oftwo cache blocks and an address translation table stored in the localmemory in the embodiment;

FIG. 6 is a diagram that schematically shows the structure of theaddress translation table in the embodiment;

FIG. 7 is a flowchart that shows the procedure of a branch resolutionroutine in the embodiment;

FIG. 8 is a diagram that schematically shows the relationships between afirst bank, a second bank, a third bank, a fourth bank, inter-bankreference tables and a generation number table in the embodiment;

FIG. 9 is a flowchart that shows the procedure for the replacement of abranch resolution routine activation instruction in the embodiment;

FIG. 10 is a diagram that schematically shows the states of a link stackduring function calls and return processes in the embodiment;

FIG. 11 is a flowchart that shows the procedure for returning theprocess from a called function in function call processing in theembodiment; and

FIG. 12 is a flowchart that shows the procedure of bank invalidationprocessing in the embodiment.

DETAILED DESCRIPTION OF THE INVENTION

The invention will now be described by reference to the preferredembodiments. This does not intend to limit the scope of the presentinvention, but to exemplify the invention.

FIG. 1 shows the configuration of an information processing apparatusaccording to an embodiment. An information processing apparatus 10comprises a processor unit 12, which includes a processor 14, a localmemory 16 and a register 18, a main memory 20, a storage apparatus 22,and an input/output apparatus 24, and these components perform datatransmission between one another via a bus 28. The processor unit 12 mayactivate DMA (Direct Memory Access) in an MFC (Memory Flow Controller)to which the unit connects in order to perform data transmission, butthe illustration therefor is omitted in FIG. 1

Although two processor units 12 are illustrated in FIG. 1, the number ofthe processor units 12 is not limited to two and may also be one orabove two. Also, each of the processors 14 may perform an equal functionso as to perform multiple processes or threads in parallel, or there maybe included a processor performing a certain function, such as a graphicprocessor or an I/O processor.

The processor 14 in the processor unit 12 executes a program includingapplication software activated by a user. The local memory 16 isconfigured, for example, with an SRAM (Static Random Access Memory)capable of high-speed access and arranged together with the processor 14on the same chip or arranged near the processor 14; in the local memory16 are stored part of an application program loaded into the main memory20, data necessary for processing or data resulting from processing, asneeded. The register 18 may be a common register which temporarilyretains a value necessary for processing in the processor 14. In thepresent embodiment, the register 18 also stores data or stacks formanaging programs stored in the local memory 16.

The main memory 20 is configured, for example, with a DRAM (DynamicRandom Access Memory) and stores the entirety of a program including anapplication activated by a user. The main memory 20 may also perform afunction as a shared memory for exchanging data between multipleprocessor units 12, or a function as a system memory for operating anOS. The storage apparatus 22 may be a common storage apparatus, such asa hard disk, or recording media such as CD-ROMs and a drive therefor, ormay be a combination of such apparatuses. The storage apparatus 22stores application programs, data necessary for processing, and data tobe saved during or at the end of processing. The input/output apparatus24 inputs a user's instruction for the information processing apparatus,such as activation of an application, or outputs a processing result.The input/output apparatus 24 may be configured with an input apparatussuch as a keyboard, a controller or a pointing device, and an outputapparatus such as a display apparatus, a speaker or a printer, or may beconfigured with combinations thereof.

In the present embodiment, a program stored in the storage apparatus 22is once loaded into the main memory 20, and part of the program is thenloaded therefrom into the local memory 16 according to the processingperformed by each processor unit 12. Accordingly, the processor 14 neednot re-access the main memory 20 each time the program advances, andaccesses to be performed can be limited within the processor unit 12 toa maximum extent, thereby enabling high-speed software processing.Conventionally, it has been necessary in such case to divide the programinto modules having sizes storable in the local memory 16 and todescribe a program for loading such modules into the local memory 16 atthe stage of programming.

Accordingly, it has been desired that such process becomes moreefficient, particularly when creating or debugging a large andcomplicated program for providing advanced functions, such as gamesoftware or simulation software. In consideration thereof, the presentembodiment provides a compiler for caching an instruction automatically.Accordingly, loading of modules into the local memory 16 need not beconsidered in programming, thereby reducing the burden on programmers.More specifically, when a program runs to an instruction that is notfound in the local memory 16, the runtime routine of the compilerautomatically performs the following processes:

-   (1) predicting an unnecessary instruction to delete it from the    local memory 16; and-   (2) loading a necessary instruction from the main memory 20 into the    local memory 16.

FIG. 2 schematically shows the structure of data stored in the localmemory 16 and the main memory 20. Into the main memory 20, a programcompiled by the complier of the present embodiment is loaded from thestorage apparatus 22. When compiling a program, the compiler of thepresent embodiment divides the program according to a certain rule so asto create program blocks. A program is loaded from the main memory 20into the local memory 16 in units of such blocks. The data size for eachof the blocks is naturally up to the capacity of the local memory 16.Hereinafter, this block will be referred to as a cache block 42.Consequently, the main memory 20 stores multiple cache blocks 42 asprograms, as shown in FIG. 2.

A program constituting one cache block 42 may be provided, for example,by dividing a sequential program at dividable positions so as to be of asize within a certain range, or by setting, according to empirical rulesor the likes in advance, a group of functions that are referred tointensively and then extracting such functions from the original programwhen compiling it. Alternatively, cache blocks 42 may be provided byonce dividing a program into basic blocks, which are larger units thanfunctions, and then reforming the blocks in consideration of the size orprocessing content. The basic block here may be provided by combiningfunctions, the minimum dividable units, or the likes according to theprocessing content, etc. Although it is desirable in any case that thecompiler automatically creates cache blocks, a programmer may manuallyspecify the ranges of cache blocks by calling functions or dividingpositions set in advance so that the programmer's intention can bepartly reflected.

As stated previously, in the local memory 16 is stored at least onecache block 42 loaded from the main memory 20, that is, at least onecopy 32 of a cache block. Since a copy 32 of a cache block is part of aprogram, there may be a need, during processing with reference to a copy32 of a cache block, to branch to an instruction or to call a functionin a copy 32 of another cache block. If the copy 32 of the cache blockof the branch target does not exist in the local memory 16 in such case,the corresponding cache block 42 in the main memory 20 is identified andcopied into the local memory 16 through a routine provided by thecompiler. The routine for performing such processing is referred to as abranch resolution routine. The specific procedure of the branchresolution routine will be described later.

The local memory 16 is provided with n storage areas defined as a firstbank 30 a, a second bank 30 b, . . . , and an nth bank 30 n. Copies 32of cache blocks loaded from the main memory 20 are serially stored inthe storage areas starting with the top address of the first bank 30 a.When there is caused a shortage of unused areas as the storing proceeds,i.e. when a copy 32 of a cache block cannot be newly stored in the nthbank 30 n, which is the last bank, all the copies 32 of cache blockspreviously stored in the first bank 30 a are discarded (hereinafter suchprocessing will be called “bank invalidation”), and copies 32 of newcache blocks are then serially stored therein. Thereafter, the secondthrough nth banks 30 b-30 n are serially invalidated and reused.

As shown in FIG. 2, the local memory 16 also stores an addresstranslation table 34, an inter-bank reference table 38 and a generationnumber table 39, besides copies 32 of cache blocks. The addresstranslation table 34 relates an address in the main memory 20 at which acache block 42 is stored, to an address in the local memory 16 at whicha copy of the cache block is stored; the table is referred to when theprocessor 14 identifies the address of a copy 32 of a cache block of abranch target in the local memory 16 to refer to the copy, or when theprocessor 14 determines whether or not a copy 32 of a necessary cacheblock exists within the local memory 16.

One inter-bank reference table 38 is provided for each of the first bank30 a, second bank 30 b, . . . , and the nth bank 30 n; when theinter-bank reference table 38 for the second bank 30 b is considered asan example and when a copy 32 of a cache block stored in another bank,the nth bank 30 n for example, provides a branch to a copy 32 of a cacheblock stored in its own bank, i.e. the second bank 30 b, the inter-bankreference table 38 stores the position of the branch instructionsequence described in the copy 32 of the cache block providing thebranch. The generation number table 39 retains a number called ageneration number with respect to each bank, and the number isincremented each time the corresponding bank is invalidated. Byreferring to an inter-bank reference table 38 and the generation numbertable 39, it can be found, for example, that a bank storing a copy 32 ofa cache block of a branch target has been invalidated, so that theaddress in the local memory 16 that has been used as the branch targetbecomes invalid.

FIG. 3 shows the configuration of a compiler for creating a cache blockto be loaded into the main memory 20 and executing a branch resolutionroutine. Each of the elements represented by functional blocks forperforming various processes shown in FIG. 3 can be implemented by aCPU, a memory, an LSI or the like in terms of hardware, and by a programor the like in terms of software. Accordingly, it will be obvious tothose skilled in the art that these functional blocks may be implementedin a variety of forms by hardware only, software only or a combinationthereof, and the form is not limited to any of them. For example, acompiler 100 may be configured with part of the information processingapparatus 10 into which the corresponding software is loaded.

The compiler 100 comprises a compile unit 102 for creating cache blocks42 from a program, and a branch resolution routine execution unit 110for executing a branch resolution routine. The compile unit 102includes: a program division unit 104 for dividing a program accordingto a certain rule as set forth previously; an instruction embedding unit106 for embedding in a program an instruction for activating a branchresolution routine, etc. for the case where the process branches toanother cache block 42; and a branch target information addition unit108 for adding, to a cache block providing a branch, information on acache block 42 of the branch target that is necessary for the executionof a branch resolution routine in each branch processing. Theinformation added by the branch target information addition unit 108will be described later.

The branch resolution routine execution unit 110 executes a branchresolution routine, which is activated by an instruction embedded by theinstruction embedding unit 106. The branch resolution routine executionunit 110 may be substantially the processor 14, as the unit operatesduring the execution of a program activated by a user on the informationprocessing apparatus 10.

In the following, the configurations of the cache blocks 42, addresstranslation table 34, inter-bank reference table 38 and generationnumber table 39 shown in FIG. 2 will be detailed. FIG. 4 schematicallyshows the structure of two cache blocks 42 a and 42 b stored in the mainmemory 20. It is assumed here that processing in the cache block 42 abranches to processing in the cache block 42 b.

The cache block 42 a created by the compiler 100 consists of a programbody 44 obtained through the division of a program by the programdivision unit 104, and a branch target table 46, which is informationadded by the branch target information addition unit 108 of the compiler100. This configuration is the same in each cache block 42. If a programdescribed in the program body 44 includes a branch to another cacheblock 42, the information on the branch will be stored in the branchtarget table 46, in which one entry is provided for each branch.

Each entry in the branch target table 46 includes a branch target cacheblock address field 52, a branch target cache block size field 54, abranch target instruction offset field 56, and a branch type field 58. Abranch target cache block address field 52 contains the top address ofthe cache block 42 b, which stores an instruction of the branch target,in the main memory 20, so that “X” is provided in the field in theexample of FIG. 4. A branch target cache block size field 54 containsthe data size of the cache block 42 b, so that “S” is provided in thefield in the example of FIG. 4. Hereinafter, an address in the mainmemory 20 may be referred to as a “main address” while an address in thelocal memory 16 may be referred to as a “local address”, so as todistinguish between the two.

A branch target instruction offset field 56 contains an offset valuefrom the top main address of the cache block 42 b to the main address atwhich the branch target instruction is described. In the example of FIG.4, when it is assumed that the branch target instruction is described inthe position indicated with a dotted line 50 at a main address “Y”, theoffset value is “Y-X”. A branch type field 58 contains information foridentifying the type of a branch, providing whether the branch is asimple branch or a function call. In the example of FIG. 4, “0” and “1”are assumed as the information, and “0” is provided in the field.

As stated previously, when a cache block 42 a includes in its programbody 44 a branch instruction to another cache block 42 b, theinstruction embedding unit 106 of the compiler 100 creates aninstruction sequence 48 for performing the branch processing in thelocal memory 16 and embeds the instruction sequence in the program body44. The instruction sequence 48 includes an instruction sequence forstoring in the register an address in the local memory 16, i.e. a localaddress, at which an entry of the branch target table 46 providing thecorresponding branch is described, and also includes an instructionsequence for activating a branch resolution routine mentionedpreviously. In FIG. 4, the former sequence is described as “rx=PC+B−A”,and the latter as “call runtime routine”.

In the sequence above, “rx” represents a value in the register, and “PC”represents a local address of the instruction sequence 48 at the timewhen the cache block 42 a is copied into the local memory 16. Theaddress in the local memory 16 at which the corresponding entry in thebranch target table 46 is provided can be obtained by adding to “PC”,the local address of the instruction sequence 48, the offset value from“A” to “B”, i.e. “B-A”, in which “A” represents the main address of thecreated instruction sequence, and “B” represents the main address of theentry.

The instruction sequence 48 may also includes an instruction forperforming processing in the case where the process returns from afunction call but a copy 32 of the cache block of the return destinationhas been discarded in the local memory 16. This processing will bedescribed later.

If a cache block 42 is formed with a group of functions included in theoriginal program, or a group of basic blocks provided by dividing theoriginal program, as set forth previously, there can be a case where thebranch source and the branch target are both included in a single cacheblock 42. In such case, the branch target information addition unit 108need not provide an entry for the branch in the branch target table 46.Also, the instruction embedding unit 106 embeds, as the instructionsequence 48, an instruction providing a simple branch to the localaddress of the branch target, not an instruction sequence for storing inthe register the local address of the branch target table 46 or aninstruction sequence for activating a branch resolution routine. Thiscan be implemented, for example, with an instruction causing a branch toan address provided by adding “PC”, the local address of the instructionsequence 48, to the offset value of the main address of the branchtarget.

FIG. 5 schematically shows the structure of copies 32 a and 32 b,provided in the local memory 16, of the two cache blocks 42 a and 42 bin the main memory 20 shown in FIG. 4, and the address translation table34. The address translation table 34 consists of an address translationtable header portion 34 a and address translation table entry portions34 b and 34 c. As will be described later, when cache blocks 42 a and 42b are loaded from the main memory 20 into the local memory 16, areas forstoring copies 32 a and 32 b of the cache blocks are ensured before theaddress translation table entry portions 34 b and 34 c are written intothe top areas therein, and the copies 32 a and 32 b of the cache blocksare then stored in the subsequent areas.

The address translation table 34 of the present embodiment is structuredas a hash table so that, based on the addresses of cache blocks 42 a and42 b in the main memory 20, the local addresses of copies 32 a and 32 bof the cache blocks can be efficiently specified. Accordingly, theaddress translation table header portion 34 a stores pointers to theaddress translation table entry portions 34 b and 34 c provided forcopies 32 a and 32 b of cache blocks desired, using addresses in themain memory or part of them as an index. The address translation table34 in such instance will be detailed with reference to FIG. 6. Theaddress translation table 34 may be of any structure other than a hashtable as long as an address in the local memory 16 can be identifiedfrom an address in the main memory 20 by means of the table.

A copy 32 a of a cache block also includes a program body 62 and abranch target table 64, and data to be retained therein is almost thesame as that in a cache block 42 a in the main memory 20. However, whenthe loading of the cache block 42 b of the branch target is completedand the storage area for the copy 32 b of the cache block is determinedin the local memory 16, the branch resolution routine replaces theinstruction sequence 48, which has called the routine itself, with abranch instruction sequence 66 that provides a branch to the branchtarget instruction. When “Y′” is the address at which the branch targetinstruction is described in the copy 32 b of the cache block of thebranch target in FIG. 5, the corresponding instruction in theinstruction sequence 66 described in the copy 32 a of the cache block ofthe branch source is replaced with the instruction “Jump to Y′”.Consequently, when the process reaches the same branch instructionthereafter, a branch to the appropriate address can be provided withoutthe involvement of the branch resolution routine.

FIG. 6 schematically shows the structure of the address translationtable 34. As stated previously, the address translation table 34includes the address translation table header portion 34 a and addresstranslation table entry portions 34 b-34 h. When a branch resolutionroutine is executed and a cache block 42 is newly loaded into the localmemory 16, the address translation table 34 is updated while the storagearea for the cache block is ensured. The address translation table 34 isupdated also when a loaded copy 32 of a cache block is discarded.

The address translation table header portion 34 a includes fields, eachof which is provided with respect to, for example, every some low-orderbits of an address in the storage area for a cache block 42 in the mainmemory 20. When a cache block 42 that is stored in the main memory 20 atan address corresponding to one of the fields is loaded into the localmemory 16, the local address of the created address translation tableentry portion 34, the portion 34 bfor example, is written into thecorresponding field in the address translation table header portion 34a.

Since each field in the address translation table header portion 34 acorresponds to part of an address in the main memory 20, there can be acase where multiple cache blocks 42 stored at multiple addresses in themain memory 20 that correspond to the same field in the addresstranslation table header portion 34 a are loaded, such as the addresstranslation table entry portions 34 b and 34 c illustrated in FIG. 6.Accordingly, each of the address translation table entry portions 34b-34 h stores, besides the address of the respective corresponding cacheblocks 42 in the main memory 20, a pointer to the local address ofanother address translation table entry portion, as indicated by arrows70 and 72 of solid lines and an arrow 74 of a dotted line in FIG. 6.

More specifically, the address translation table entry portion 34 fretains: the address of the cache block 42 corresponding to the portionitself in the main memory 20; the local address of the addresstranslation table entry portion 34 g connected posterior to the portion34 f in relation to the address translation table header portion 34 a,as indicated by the arrow 70 of a solid line; the local address of theaddress translation table entry portion 34 e connected anterior to theportion 34 f, as indicated by the arrow 72 of a solid line; and thelocal address of the address translation table entry portion 34 dprovided for the cache block 42 that has been loaded subsequent to thecache block 42 corresponding to the portion 34 f in chronological order,as indicated by the arrow 74 of a dotted line. If each of the addresstranslation table header portion 34 a and the address translation tableentry portions 34 b-34 h has no entry connected thereto, a constant willbe assigned instead of an address.

By configuring such table, a copy 32 of a desired cache block in thelocal memory 16 can be efficiently specified based on an address in themain memory 20. To the procedure for adding a new address translationtable entry portion to the address translation table 34, a common methodfor adding an entry to a hash table can be applied.

Next, there will be described a branch resolution routine performedusing the apparatus and data structure described above. FIG. 7 is aflowchart that shows the procedure of a branch resolution routine. Thedescription will be made on the assumption that a user has instructedthe information processing apparatus 10 to activate software via theinput/output apparatus 24 or the like, cache blocks 42 corresponding tothe software have been loaded into the main memory 20, at least one ofthe cache blocks 42 has been loaded into the local memory 16, and theprocessor 14 has been performing processing with reference to the atleast one of the cache blocks.

When the process advances to an instruction for calling a branchresolution routine in a copy 32 of a cache block and the branchresolution routine is called accordingly, the processor 14, which is theentity of the branch resolution routine execution unit 110, refers tothe corresponding entry in the branch target table 64 based on theaddress that has been stored in the register 18 through the precedinginstruction sequence, and acquires the top address of the cache block 42of the branch target in the main memory 20, the size of the cache block,the offset value of the branch target instruction, and the type of thebranch (S20). The processor 14 then refers to the address translationtable 34 to check if the table contains an entry retaining the addressin the main memory 20 (S22). If the table does not contain such entry (Nat S22), the processor 14 will determine that a copy 32 of the cacheblock is not included in the local memory 16 and will initiate theloading.

More specifically, the processor 14 checks if there is an enough unusedarea in the bank where the latest loading of a copy 32 of a cache blockhas been made, the first bank 30 a for example, to store a copy 32 of anew cache block and an address translation table entry portion therefor,the address translation table entry portion 34 b for example (S24). Insuch occasion, if the bank to be used next, i.e. the second bank 30 b,is not used yet, it is determined that there is an enough unused area.If there is no enough area (N at S24), i.e. if a copy 32 of a cacheblock stored in the next bank, the second bank 30 b, need be discardedto store a copy 32 of the new cache block, invalidation of the secondbank 30 b will be performed (S26). The invalidation processing will bedescribed later.

If an area for storing a copy 32 of the new cache block is ensured (Y atS24 or S26), an entry will be added to the address translation table 34by creating and writing the address translation table entry portion 34 bin the top of the area and updating the address translation table headerportion 34 a (S28). Then, based on the address in the main memory 20acquired in S20, the cache block 42 is loaded from the main memory 20into the ensured area in the local memory 16 (S30).

Thereafter, the instruction sequence that has called the branchresolution routine in the copy 32 of the cache block of the branchsource, which has been originally processed, is replaced with a branchinstruction that provides a branch to the corresponding instruction inthe copy 32 of the cache block newly loaded (S32). The address of theinstruction sequence of the branch target in the local memory 16 (“Y′”in FIG. 5) is obtained by adding the offset value of the instructionsequence acquired in S20 to the top local address of the copy 32 of thecache block loaded (“X′” in FIG. 5). The process is then caused tobranch to the branch target instruction in the copy 32 of the cacheblock (S34).

If the address translation table 34 contains the corresponding entry inS22 (Y at S22), it means that a copy 32 of the cache block of the branchtarget exists within the local memory 16. Accordingly, the local addressof the address translation table entry portion 34 b is acquired from theaddress translation table 34 to perform processing of S32 and S34. In abranch resolution routine, a copy 32 of a cache block of a branch targetcould exist in the local memory 16 if the copy 32 of the cache block hasbeen stored in the local memory 16 through a previous branch resolutionroutine caused by another instruction sequence.

In the following, there will be described a method for managing thefirst through nth banks 30 a-30 n that store copies 32 of cache blocksin the local memory 16. FIG. 8 schematically shows the relationshipsbetween the first bank 30 a, second bank 30 b, third bank 30 c, fourthbank 30 d, inter-bank reference tables 38 a, 38 b, 38 c and 38 d relatedto the respective banks, and the generation number table 39. Arrowsillustrated in FIG. 8 show the correspondence relationships betweenthem.

As stated previously, cache blocks 42 of branch targets are loaded intothe local memory 16 one after another during execution of a program inthe present embodiment. Accordingly, if the amount of code necessary forthe execution of the program exceeds the capacity of the local memory16, more strictly the capacity available for storing copies 32 of cacheblocks, there will be eventually a need to discard copies 32 of cashblocks already loaded so as to reuse the area as the storage area forcopies 32 of new cache blocks.

The problem there is that branch instructions providing branches tocopies 32 of cache blocks to be discarded may be found ubiquitously inall the copies 32 of cache blocks in the local memory 16. The addressesof the branch targets in the local memory 16 included in such branchinstructions are made invalid at the time when the cache blocks of thebranch targets are discarded. Accordingly, the branch instructions inthe copies 32 of such cache blocks of the branch sources, which havebeen provided in S32 in FIG. 7, need be replaced again with branchresolution routine activation instructions. To perform such processingefficiently, the area for storing copies 32 of cache blocks is dividedinto n banks of the first through nth banks 30 a-30 n, so as to managethe validity of copies 32 of cache blocks in units of banks. Each of theinter-bank reference tables 38 a, 38 b, 38 c and 38 d is used, when thecorresponding bank is invalidated, to specify the address of a branchinstruction that is to be replaced by a branch resolution routineactivation instruction in a copy 32 of a cache block of a branch source.

Although FIG. 8 shows only four banks of the first through fourth banks30 a-30 d, the same configuration can be employed also in the case wherethe number of the banks is other than four. Each of the inter-bankreference tables 38 a-38 d includes a branch instruction address field72 and a generation number low-order bit field 74. A branch instructionaddress field 72 contains the local address of an instruction sequence,which includes an instruction providing a branch to a copy 32 of a cacheblock stored in the corresponding bank, included in a copy 32 of thecache block of the branch source. The instruction sequence described atthat local address should be replaced with a branch resolution routinewhen the corresponding bank is invalidated.

A generation number low-order bit field 74 contains the leastsignificant bit of the generation number of a bank that stores a copy 32of a cache block containing an instruction sequence including a branchinstruction. The generation number stored here is a generation number ofa bank of a branch source at the time when the corresponding entry isregistered in the inter-bank reference tables 38 a-38 d. Hereinafter,this generation number is called “generation number of an entry”. When abranch resolution routine is activated in a copy 32 of a cache block andthe corresponding instruction is replaced with a branch instructionproviding a branch to a copy 32 of a cache block stored in the bankcorresponding to the table, an entry is additionally registered in theinter-bank reference tables 38 a-38 d through the branch resolutionroutine.

If a copy 32 of the cache block of the branch source and a copy 32 ofthe cache block of the branch target are included in the same bank,since these copies will be invalidated at the same time, the address ofthe branch source need not be added to the inter-bank reference tables38 a-38 d. Accordingly, only when a copy 32 of the cache block of thebranch target exists in a different bank, additional registration ismade in the inter-bank reference table for the bank, among the tables 38a-38 d, through the branch resolution routine activated in the branchsource.

The generation number table 39 includes a field corresponding to each ofthe first through fourth banks 30 a-30 d, which contains the currentgeneration number of the corresponding bank. The generation number isincremented by one each time the corresponding bank is invalidated. Inthe example of FIG. 8, the generation numbers of the first bank 30 a andsecond bank 30 b are “3”, and those of the third bank 30 c and fourthbank 30 d are “2”. When branch instructions providing branches to theaddress “X” in the second bank 30 b are described at the local address“A” in the third bank 30 c and the local address “B” in the fourth bank30 d, as also shown in FIG. 8, branch instruction address fields 72 ofthe inter-bank reference table 38 b provided for the second bank 30 bcontain “A” and “B”, while generation number low-order bit fields 74 ofthe table contain “0” as the least significant bit of “2”, which is thegeneration number of the third bank 30 c containing the local address“A” and is also the generation number of the fourth bank 30 d containingthe local address “B”.

Each entry stored in the inter-bank reference tables 38 a-38 d is usedwhen the corresponding bank among the first through fourth banks 30 a-30d is invalidated and a branch instruction in a copy 32 of a cache blockof a branch source is replace with a branch resolution routineactivation instruction accordingly. However, if the bank storing thecopy 32 of the cache block of the branch source has been alreadyinvalidated before invalidating the subject bank, the entry itself makesno sense, i.e. the entry is invalid. Accordingly, to determine thevalidity of each entry stored in the inter-bank reference tables 38 a-38d, the generation number low-order bit fields 74 are used.

When the generation number of an entry in the inter-bank referencetables 38 a-38 d is equal to the current generation number of a bankthat includes or included the branch instruction corresponding to theentry, the entry is valid; when they are not equal, it means that a copy32 of a cache block including the branch instruction has been discarded,and hence, the entry is invalid. In the present embodiment, a generationnumber of an entry is compared with a current generation number usingthe least significant bits of the numbers, as will be described later

Next, there will be described the procedure for the replacement of abranch resolution routine activation instruction shown as S32 in FIG. 7,which includes additional registration of an entry in the inter-bankreference tables 38 a-38 d. FIG. 9 is a flowchart that shows theprocedure for the replacement of a branch resolution routine activationinstruction. First, if a branch to a different bank is provided, such aswhen a copy 32 of a cache block of a branch target is newly stored in adifferent bank (Y at S68), an invalid entry will be sought in thecorresponding inter-bank reference table 38 of the bank (hereinafterreferred to as “branch target bank”), e.g. in the inter-bank referencetable 38 b when the branch target bank is the second bank 30 b in FIG. 8(S70). If there is an invalid entry, such entry is overwritten to add anew entry. If the copy 32 of the cache block of the branch target isincluded in the same bank (N at S68), the processing of S70-S76 will notbe performed as updating of inter-bank reference tables is unnecessary.

The validity of an entry is basically determined by comparing thegeneration number of the entry with the current generation number of abank that includes a branch instruction for the entry, as mentionedpreviously. For the determination, in the present embodiment are usedthe least significant bit of the generation number of each entry, whichis stored in a generation number low-order bit field 74 of an inter-bankreference table 38, and the bank number, provided as the first throughnth, of a bank that includes a branch instruction for the entry(hereinafter referred to as “branch source bank”). A bank number can becomputed from the local address of a branch instruction stored in thebranch instruction address field 72 of each entry.

A bank that has stored a copy 32 of a cache block most lately is nowdefined as a reference bank. Since the generation number of each bank isincremented by one when the bank is invalidated, the reference bank is abank of which generation number has been incremented most recently amongthe first through nth banks 30 a-30 n. If the values in the generationnumber table 39 in FIG. 8 are considered, for example, the second bank30 b will be the reference bank. In such case, the first bank 30 a,which precedes the second bank 30 b and has a smaller bank number thanthe second bank 30 b defined as the reference bank, has a generationnumber identical with that of the second bank 30 b; the third bank 30 cor fourth bank 30 d, which follows the second bank 30 b and has agreater bank number than the second bank 30 b, has a generation numbersmaller by one than that of the second bank 30 b defined as thereference bank.

With such characteristic, if the bank number of a branch source bankprovided in an entry of an inter-bank reference table 38 is smaller thanthe bank number of the reference bank, the current generation number ofthe branch source bank is identical with that of the reference bank. Insuch case, it is determined that an entry that stores in its generationnumber low-order bit field 74 a value identical with the leastsignificant bit of the generation number of the reference bank is valid,while an entry that stores in its generation number low-order bit field74 a value not identical with the least significant bit of thegeneration number of the reference bank is invalid. On the other hand,if the bank number of the branch source bank is greater than that of thereference bank, the current generation number of the branch source bankis smaller by one than that of the reference bank. In such case, it isdetermined that an entry that stores in its generation number low-orderbit field 74 a value not identical with the least significant bit of thegeneration number of the reference bank is valid, while an entry thatstores in its generation number low-order bit field 74 a value identicalwith the least significant bit of the generation number of the referencebank is invalid.

Such determination process is repeated for each entry until an invalidentry is detected. Consequently, the generation number of an entry canbe compared with the current generation number of a bank correspondingto the entry without searching the generation number table 39, by onlyusing the least significant bit of the generation number of thereference bank and that of the generation number of the entry. Also, thecurrent generation number of a bank corresponding to each entry may besought in the generation number table 39 so as to be directly comparedwith a value stored in a generation number low-order bit field 74. Bystarting a search in the same inter-bank reference table 38 b from anentry next to the invalid entry detected the last time, the searchprocess can be made more efficient.

If an invalid entry is detected (Y at S72), the branch instructionaddress field 72 of the entry will be overwritten with the address atwhich the branch resolution routine activation instruction currentlyexecuted is described, and the generation number low-order bit field 74of the entry will be overwritten with the current generation number ofthe bank that stores the copy 32 of the cache block including the branchresolution routine activation instruction, so that the entry will benewly registered in the inter-bank reference table 38 (S76). If noinvalid entry is detected (N at S72), priority will be given to theentry to be added, so that one of the entries already registered will beselected and overwritten therewith. Prior thereto, the branchinstruction described at the address stored in the branch instructionaddress field 72 of the selected entry is replaced with a branchresolution routine activation instruction (S74). Then, the new entry isregistered in the inter-bank reference table 38 (S76).

Next, based on the identification information regarding the type of thebranch stored in the branch type field 58 of the branch target table 64,which is acquired in S20 of FIG. 7, it is determined whether theinstruction to be provided as a replacement is a branch instruction or afunction call instruction (S78). If it is a branch instruction (N atS78), the branch resolution routine activation instruction will bereplaced with the branch instruction (S80) ; if it is a function callinstruction (Y at S78), the branch resolution routine activationinstruction will be replaced with the function call instruction (S82). Afunction call instruction will be described later. Thus, when a copy 32of a cache block is newly stored in a bank, such as the second bank 30b, additional registration can be made in the inter-bank reference table38 b or the like and a branch instruction to the copy 32 of the cacheblock can be provided as a replacement through the process stated above.

A function call is different from a simple branch, requiring the returnto the original program. When a branch resolution routine is replacedwith a function call instruction in S82 of FIG. 9, the branch processingfor providing a branch to the branch target instruction as shown in S34of FIG. 7 requires, prior to the branch, processing for storing in theregister 18: the top address of the storage area for the cache block 42of the source of the call, which contains an instruction sequence towhich the process returns from the function, in the main memory 20; thesize of the cache block 42; and the offset value from the top address tothe address at which the instruction of the return destination isdescribed. Accordingly, a function call instruction provided as areplacement in S82 of FIG. 9 also includes an instruction for executingsuch processing. The values to be stored in the register 18, as setforth above, can be acquired with reference to the branch target table64 for the copy 32 of the cache block.

With regard to a branch for returning the process from a calledfunction, on the other hand, the source of the function call is notnecessarily one. Therefore, it is unable to provide, as a replacement, abranch instruction in which the address of the branch target in thelocal memory is specified, as described so far. Accordingly, withrespect to each branch for returning the process from a function, theaddress of a cache block 42 to which the process returns in the localmemory 16 may be acquired by searching the address translation table 34based on the address of such cache block in the main memory 20, which isstored in the register 18. In the present embodiment, however, a linkstack is used so as to improve the processing efficiency. A link stackis a stack to be referred to when a function is called and the processis then returned from a copy 32 of a cache block of the branch target toa local address in a copy 32 of a cache block of the source of the call.

Also, there is a case in the present embodiment where a copy 32 of acache block including an instruction sequence of the return destinationis discarded or re-loaded into another area while processing at thebranch target is performed. Such case can be recognized when the processreturns, by invalidating the corresponding address stored in the linkstack.

FIG. 10 schematically shows the states of a link stack during functioncalls and return processes. Link stacks 36 a-36 e show the time-seriesvariation of a single link stack stored in the register 18. Copies 32c-32 e of cache blocks are to be serially processed according tofunction calls, in which the copy 32 c calls the copy 32 d, and the copy32 d then calls the copy 32 e. A link stack may be created for eachthread processed by the information processing apparatus 10, but here isshown only a single link stack.

It is assumed here that the link stack 36 a is in the initial state. Thelink stack 36 a stores addresses “E4”, “E3”, “E2” and “E1” of returndestinations in copies 32 of cache blocks (not illustrated) in thisorder. When the processing in the cache block 32 c is performed in thisstate and the process is then caused to branch to an address “C1” in thecache block 32 d by an instruction “call C1” (S10), an address “R1” inthe cache block 32 c to which the process will return is added to thelink stack 36 a (link stack 36 b). Subsequently, the processing in thecache block 32 d is performed and when the process is caused to branchto an address “C2” in the cache block 32 e by an instruction “call C2”(S12), an address “R2” in the cache block 32 d to which the process willreturn is added to the link stack 36 b (link stack 36 c).

Then, the processing in the cache block 32 e is performed and when theprocess returns to the cache block 32 d according to an instruction“return” (S14), the link stack 36 c is referred to, so that the returndestination address “R2” can be found in the top entry therein.Consequently, the link stack becomes the state shown as the link stack36 d. Thereafter, the processing in the cache block 32 d is performedand when the process returns to the cache block 32 c according to aninstruction “return” (S16), the link stack 36 d is referred to, so thatthe return destination address “R1” can be found in the top entrytherein. As shown in FIG. 10, when there is caused a shortage in thecapacity of the link stacks 36 a-36 e, the oldest entry is deleted.

If the link stacks 36 a-36 e include an address in a copy 32 of a cacheblock that is discarded during branch processing, such address will bereplaced with an invalid address. The invalid address here is anarbitrary value at which no instruction can be placed. While the copy 32e of the cache block is executed, for example, if the copy 32 d of thecache block of the return destination is discarded, the “R2” in the topentry of the link stack 36 c will be replaced with “0” or the like.Thus, it can be recognized that the copy 32 of the cache blockcontaining the return destination address has been discarded.

When a copy 32 of a cache block of a return destination is discarded, abranch resolution routine is activated so as to re-load such cache blockfrom the main memory 20 based on the information that has been stored inthe register 18 before the function call. Also, instead of an invalidaddress, the address in the main memory 20 or local memory 16 at whichthe branch resolution routine is stored may be assigned in the linkstack. Accordingly, the process is caused to branch to such address,thereby activating the branch resolution routine directly. Thus, theprocessing for determining the discard of a copy 32 of a cache blockbased on whether or not the corresponding address is invalid can beomitted.

FIG. 11 is a flowchart that shows the procedure for returning theprocess from a called function using the link stacks 36 a-36 e asmentioned previously. First, the top entry of, for example, the linkstack 36 c is acquired, as shown in FIG. 10 (S40). Then, it isdetermined if the top entry thus acquired is included within an addressrange where the corresponding copy 32 of the cache block is stored inthe local memory 16 (S42). If the entry is included within the addressrange (Y at S42), it will be determined that the copy 32 of the cacheblock containing the instruction sequence of the return destination hasnot been discarded, so that the process will be caused to branch to thereturn destination instruction described at the acquired address (S44).

If the top entry is “0” or another address that is not included withinthe address range (N at S42), whether or not the corresponding copy 32of the cache block is included in the local memory 16 will be firstchecked by searching the address translation table 34 based on theaddress of the cache block in the main memory 20 stored in the register18 (S46). It is because, even if the entry is not included within theaddress range, there is a case where the copy 32 of the cache block oncediscarded has been re-loaded, or a case where the entry has been deleteddue to a shortage in the capacity of the link stack but the copy 32 ofthe cache block itself still exists. Accordingly, if the correspondingentry is found in the address translation table 34 (Y at S48), theaddress of the corresponding copy 32 of the cache block in the localmemory 16 is acquired from the table, so as to provide a branch to thereturn destination instruction based on the offset value stored in theregister 18 (S50).

If the corresponding entry is not found in the address translation table34 (N at S48), it will be determined that the copy 32 of the cache blockhas been discarded and has not been re-loaded yet, so that the loadingprocess will be initiated. More specifically, as with S24, S26, S28, S30and S34 in FIG. 7, the capacity of an unused area in a bank is checked(S52), a bank is invalidated if necessary (S54), registration is made inthe address translation table 34 (S56), the cache block 42 is loaded(S58), and a branch is provided to the return destination instruction(S60). Accordingly, even if a copy 32 of a cache block including areturn destination instruction has been once discarded, the loadingprocess can be performed only when necessary after an efficient search.

FIG. 12 is a flowchart that shows the procedure for invalidating a bank,and the second bank 30 b is considered here as an example. First, avalid entry is extracted from the inter-bank reference table 38 bprovided for the second bank 30 b, which is to be invalidated, and abranch instruction described at the address stored in the branchinstruction address field 72 of the entry is replaced with a branchresolution routine activation instruction (S90). The validity of anentry can be determined using the same logic as described with referenceto FIG. 9. Then, an arbitrary address in the second bank 30 b and theleast significant bit of a generation number are provided in the branchinstruction address field 72 and generation number low-order bit field74, respectively, of each entry in the inter-bank reference table 38 b,so as to invalidate all the entries (S92).

Thereafter, based on the connections between entries in the addresstranslation table 34 provided according to the order in which theentries have been loaded, as indicated by the arrow 74 of a dotted line,an entry corresponding to a copy 32 of a cache block in the second bank30 b to be invalidated is deleted (S94). More specifically, when anentry retains a pointer to the entry to be deleted, such pointer isreplaced with a constant other than an address. Then, the generationnumber in a field corresponding to the second bank 30 b in thegeneration number table 39 is incremented by one (S96). Lastly, if thelink stacks 36 a-36 e contain an address in the second bank 30 b to beinvalidated, such address will be replaced with “0” or the like so as tobe invalidated, as stated previously (S98). Thus, invalidation of thesecond bank 30 b can be reflected in a branch resolution routine thoughthe processing above.

According to the present embodiment set forth above, a program isdivided into cache blocks, which are units by which a program is loadedinto the local memory, and the processor refers to a cache block storedin the local memory to perform processing. Therefore, the processor canrefer to a program more quickly than in the case where it accesses aprogram stored in the main memory, thus reducing the overall processingtime.

The division of a program is automatically performed by the compilerbased on the size or frequency of use. During compiling, a branchresolution routine activation instruction is also embedded to execute abranch between cache blocks within the local memory. When the branchresolution routine is activated while the program is executed, a cacheblock is loaded from the main memory, if necessary, and a branchinstruction with an address in the local memory is created and writteninto the cache block. These processes are performed by the compiler, sothat the programmer need not divide a program into modules or prepare aprogram for loading each module into the local memory. Accordingly, fastaccess to a program can be achieved with less work.

In addition, the discard of cache blocks is managed for each bank in thepresent embodiment. When a bank is invalidated to load a new cacheblock, the corresponding inter-bank reference table is used to find allbranch instructions providing branches to cache blocks stored in thebank to be invalidated, and to identify the positions of such branchinstructions in the cache blocks of the branch sources. Thereafter, thebranch instructions are replaced again with branch resolution routineactivation instructions. Unlike a common cache memory in which nocorrelation is found between data stored in cache lines, cache blocksstored in the local memory in the present embodiment have complicatedpositional correlation. Therefore, discarding a cache block once loadedmeans destroying the positional relationships established in the localmemory, thereby affecting the programs of cache blocks processedanterior or posterior to the discarded cache block. Such complicatedcondition can be efficiently controlled by managing cache blocks foreach bank in terms of generation numbers.

Also, a cache block is certainly provided with a branch target table;when the cache block includes branch processing, the branch target tablecontains information on a cache block of the branch target, morespecifically the address at which the cache block of the branch targetis stored in the main memory. In addition, since the address translationtable, which shows the relationship between an address in the mainmemory and an address of a copy in the local memory, is provided withinthe local memory, the storage area of a cache block or whether or not acopy of the cache block exists in the local memory can be identified atany time by using the address of the cache block in the main memory asidentification information. If the address translation table isstructured as a hash table, more efficient search will be achieved. Inaddition, such hash table structure enables easy tracing of the order inwhich cache blocks have been loaded into the local memory, so that anentry for a cache block that is stored in an invalidated bank can bedeleted efficiently.

When the process returns from a function to the original processing infunction call processing, a stack is used instead of performing theprocessing for replacing a branch resolution routine with a branchinstruction. Accordingly, even in function call processing in which thereturn destination cannot be fixed, a program is automatically dividedand cache blocks are loaded into the local memory in the same way as inother branch processing, and hence, the same effects can be achieved asstated above.

The present invention has been described with reference to theembodiment. The embodiment above is intended to be illustrative only andit will be obvious to those skilled in the art that variousmodifications to constituting elements or processes could be developedand that such modifications also fall within the scope of the presentinvention.

For example, although the present embodiment describes a mode in whichcache blocks obtained by dividing a program are loaded from the mainmemory into the local memory, they may not necessarily be programs aslong as they are reference data having positional or dependencerelationships between each other, such as segments of a series of datastream or pieces of frame data of a moving image that has been codedusing inter-frame prediction.

1. An information processing apparatus comprising: a main memory whichstores a plurality of data blocks having connections according to areference order in which the data blocks are referred to; a local memorywhich stores at least part of the plurality of data blocks copiedthereinto; and a processor which performs processing by seriallyreferring to the data blocks copied into the local memory according tothe reference order and which newly copies the data block from the mainmemory into the local memory if necessary, wherein: an area for storingthe data blocks in the local memory comprises a plurality of sections;and, when there is a shortage of a storage area within the local memoryinto which a data block is newly copied, the processor discards the datablocks copied previously in units of the sections to ensure a newstorage area, and stores in the local memory, with respect to each ofthe data blocks copied, reference destination information on the storagearea of a data block to be referred to posteriorly to the data block, soas to serially refer to the data blocks.
 2. The information processingapparatus according to claim 1, wherein: the processor further stores inthe local memory, with respect to each of the sections, reference sourceinformation on a data block referred to anteriorly to the data blockstored in the section; and, when discarding the data blocks copiedpreviously in units of the sections, the processor identifies a datablock referred to anteriorly to a data block to be discarded withreference to the reference source information, and performs processingfor invalidating information on the storage area of the data block to bediscarded included in the reference destination information of the datablock referred to anteriorly.
 3. The information processing apparatusaccording to claim 2, wherein: the processor further stores in the localmemory, with respect to each of the sections, the number of discard ofthe data blocks stored in the section, as a generation number of thesection; the processor further stores, as the reference sourceinformation, information on the generation number of the section inwhich the data block referred to anteriorly is stored, provided at thetime when the information on the data block referred to anteriorly isregistered; and, when the generation number of the section in which thedata block referred to anteriorly is stored, which is provided at thetime of registration and included in the reference source information,is different from the current generation number of the section, theprocessor determines invalidity of the information on the data blockreferred to anteriorly in the reference source information.
 4. Theinformation processing apparatus according to claim 3, wherein: theinformation on the generation number of the section in which the datablock referred to anteriorly is stored, which is included in thereference source information, is the least significant bit of thegeneration number; and the processor determines if the generation numberof the section in which the data block referred to anteriorly is stored,which is provided at the time of registration, is different from thecurrent generation number of the section, with reference to the leastsignificant bit of the generation number provided at the time ofregistration.
 5. An information processing apparatus comprising: a mainmemory which stores a program of software activated; a local memorywhich stores a plurality of program blocks provided by copying at leastpart of the program; and a processor which performs processing byserially referring to the program blocks copied into the local memoryaccording to an instruction in the program and which newly stores theprogram block from the main memory into the local memory if necessary,wherein: an area for storing the program blocks in the local memorycomprises a plurality of sections; when there is a shortage of a storagearea within the local memory into which a program block is newly stored,the processor discards the program blocks stored previously in units ofthe sections to ensure a new storage area; and the processor stores inthe local memory, with respect to each branch instruction, amonginstructions included in the program block stored, which provides abranch from the program block to another program block, referencedestination information on the storage area of a program block of thebranch target, so as to serially refer to the program blocks.
 6. Theinformation processing apparatus according to claim 5, wherein theprocessor writes the reference destination information into a branchinstruction, among instructions included in a program block beingprocessed, which provides a branch from the program block to anotherprogram block.
 7. The information processing apparatus according toclaim 5, wherein, when storing the program block in the local memory,the processor further stores in the local memory an address translationtable in which the address of the program block in the main memory isrelated to the address where the program block is stored in the localmemory, and acquires the reference destination information on the basisof the address translation table to store the information.
 8. Aninformation processing method, comprising: storing, in a local memory,program data of a branch source in which a branch instruction specifyingan address in the local memory is described, and program data of abranch target which contains the address specified by the branchinstruction, and relating information on the storage area of the programdata of the branch source in the local memory to the program data of thebranch target to store the information; and identifying, when theprogram data of the branch target is discarded, the program data of thebranch source on the basis of the information on the storage area of theprogram data of the branch source in the local memory, and invalidatingthe address specified by a branch instruction described in the programdata of the branch source.
 9. A computer program product, comprising: amodule which stores, in a local memory, program data of a branch sourcein which a branch instruction specifying an address in the local memoryis described, and program data of a branch target which contains theaddress specified by the branch instruction, and relates information onthe storage area of the program data of the branch source in the localmemory to the program data of the branch target to store theinformation; and a module which identifies, when the program data of thebranch target is discarded, the program data of the branch source on thebasis of the information on the storage area of the program data of thebranch source in the local memory, and invalidates the address specifiedby a branch instruction described in the program data of the branchsource.